1. Field Of The Invention
This invention relates in general to microprocessor based computer systems and, more particularly, to reset circuitry for such computer systems.
2. Related Art
Microprocessors such as the Intel 386 (TM) and i486 (TM) include a reset input to enable the microprocessor to be initialized in a known or defined state when power to the microprocessor is turned on. (386 and i486 are trademarks of Intel Corporation.) A computer employing an Intel 386 microprocessor and associated power reset circuitry is shown in FIG. 1 as computer 10. Before discussing this power reset circuitry, it is helpful to describe computer 10 in general terms.
Computer 10 is a dual bus computer which includes the aforementioned microprocessor now designated as microprocessor 100. Microprocessor 100 includes a reset input shown in FIG. 1 as RESET. Microprocessor 100 is coupled via a CPU local bus 105 to a buffer 110 which couples CPU local bus 105 to a system local bus 115. System local bus 115 is coupled via a latch/buffer/decoder 120 to a planar I/O (input/output) bus 125 to which peripheral devices such as device 130 are connected. System local bus 115 is further coupled to a memory controller and memory 135. System local bus 115 is also coupled via a buffer 140 and a Micro Channel (TM) bus 145 to Micro Channel (TM) sockets or slots 150 into which various adapter cards may be inserted. (Micro Channel is a trademark of the International Business Machines Corporation.) A direct memory access (DMA) controller 155 is coupled to system local bus 115 to facilitate direct access to memory 135 without the intervention of microprocessor 100. Computer 10 further includes a bus control and timing circuit 160 which is coupled to system local bus 115 to permit control and timing of bus 115. A central arbitration point 165 is coupled to both bus control and timing circuit 160 and Micro Channel sockets 150. Central arbitration point 165 determines which functional entity gets access to the Micro Channel bus 145, be it microprocessor 100, a bus master plugged into one of Micro Channel sockets 145 or DMA controller 155, for example.
A cache memory 170 is coupled to CPU local bus 105 and microprocessor 100 as shown. To control the operation of cache memory 170, an Intel 82385 cache controller 175 is coupled to CPU local bus 105 and system local bus 115 as shown. When computer 10 is being referred to as a dual bus computer, it is the CPU local bus 105 and the system local bus 115 which are the two busses being referenced. Each of busses 105 and 115 includes respective address, data and control busses. To facilitate the processing of floating point operations, a math coprocessor 180 is coupled to CPU local bus 105.
As mentioned earlier, microprocessor 100 includes a reset input designated RESET. Microprocessor 100 further includes a clock input designated CLK2 to which a clock frequency of double (2.times.) the microprocessor internal clock frequency is provided. The internal clock frequency of microprocessor 100 is defined to be equal to 1.times.. A divide by two and phase correction circuit 100A is included within microprocessor 100 such that the CLK2 or 2.times. clock signal (for example, at 50 MHz) provided to the microprocessor CLK2 input is divided down to 1.times. (or 25 MHz, for example) for use internal to microprocessor 100. A CLK2 generation circuit or clock oscillator 185 is provided to generate the CLK2 signal. CLK2 generation circuit 190 includes a CLK2 output which is coupled to RESET LOGIC 190, a divide by 2 circuit 195, bus control and timing circuit 160, cache controller 175, microprocessor 100 and coprocessor 180 to provide clock information thereto. Reset logic 180 includes a RESET output which is coupled to the microprocessor RESET input, math coprocessor 180, cache controller 175 and bus control and timing circuit 160 to provide an appropriate reset pulse to such devices when system reset is desired. From FIG. 1 it is seen that divider circuit 195 divides the CLK2 clock signal by 2 to produce an external clock signal designated CLK which is provided to RESET LOGIC 190 and to bus control and timing circuitry 160. It is noted that the external clock CLK signal generated at the CLK output of divider circuit 195 exhibits a frequency substantially the same as the 1.times. internal clock frequency of microprocessor 100. For this reason, the CLK signal is referred to alternatively as the 1.times. external clock signal.
An overview of the operation of the 386 microprocessor with respect to clocking operations is now presented. As mentioned above, the 386 microprocessor operates from a two-times external clock or 2.times. clock external input. Thus, a 20 MHz 386 microprocessor requires a 40 MHz external clock signal at its CLK2 input and a 25 MHz 386 microprocessor requires a 50 MHz external clock signal at its CLK2 input.
Internally, the 386 microprocessor generates its own one-times (1.times.) clock by dividing the CLK2 input signal by two. This 1.times. internal clock signal is used inside the 386 microprocessor to determine the timing of the various internal logic operations including operations which appear as microprocessor outputs. This 1.times. clock signal is also used internal to the 386 microprocessor to determine the appropriate sample time for external inputs. The timing relationship of this 1.times. internal clock signal to the CLK2 clock signal is shown in FIG. 2 in which the 1.times. internal clock signal is shown in the lowermost portion thereof and the CLK2 clock signal is shown in the uppermost portion thereof. The timing relationships relative to this 1.times. clock are documented by Intel in the 80386 Hardware Manual. The 1.times. internal clock signal is used to determine the appropriate phase of the CLK2 signal since multiple CLK2 phases are required to complete a 386 microprocessor bus cycle.
The typical 386 microprocessor based computer system will generate, external to the 386 microprocessor, its own 1.times. external clock signal since there is no 1.times. external clock output from the 386 microprocessor. As seen in FIG. 1, this external 1.times. clock signal is generated in computer 10 at the CLK output of divider circuit 195 as the CLK signal is. This 1.times. external clock signal or CLK signal is used by external logic to monitor or sample the 386 microprocessor and to control the necessary 386 microprocessor inputs.
The two separately generated 1.times. clocks, namely the internal 1.times. clock and the external 1.times. clock (CLK at divider 195) may undesirably differ in their phasing unless some means is provided to achieve synchronization of the internal 1.times. clock and the external 1.times. clock during the power up of microprocessor 100. This required synchronization action is typically provided by generation of the signal RESET which is provided to the RESET input of microprocessor 100. External logic, namely reset logic 190, triggers the active edge of the RESET signal relative to the externally generated 1.times. clock. That is, there is a known and fixed relationship between the active edge of the RESET signal and the externally generated 1.times. clock signal. The RESET signal is sampled by the 386 microprocessor on each CLK2 rising edge. The resulting RESET sample information is used by internal divide by 2 and phase correction circuitry 100A to change the phasing of the internal 1.times. clock if required to bring the internal 1.times. clock into sync with the external 1.times. clock.
To provide the computer user with a processor upgrade path in one type of computer 10, a daughter card (not shown) is provided which includes microprocessor 100, coprocessor 180, cache controller 175, cache 170 and the associated reset circuitry. This daughter card is alternatively referred to as a processor complex. The daughter card plugs into a planar board or motherboard containing the remaining components and devices of computer 10 shown in FIG. 1. In this manner, a daughter card containing a different microprocessor configuration than that originally provided with computer 10 can be plugged into the planar board to improve computer performance. An example of one computer employing such a daughter card arrangement is the IBM Personal System/2 Model 70 A21 computer. (Personal System/2 is a registered trademark of the International Business Machines Corporation.)
Microprocessor technology has advanced beyond the level of the 386 based computer 10 described above. More specifically, Intel Corporation has recently introduced the i486 microprocessor which offers significant processor performance benefits by incorporating a microprocessor, coprocessor, cache memory and cache controller on a single chip.
Unfortunately, a number of difficulties are encountered when attempting to outfit an existing computer such as computer 10 with a i486 microprocessor. It will be recalled that computer 10 includes an external 2.times. clock (CLK2), and the 386 microprocessor of computer 10 includes a CLK2 pin to which the 2.times. clock signal is provided. The 386 microprocessor further includes an internal divide by 2 circuit to produce an internal 1.times. clock. In contrast, the i486 microprocessor does not use the same internal clock phase setting approach via the microprocessor RESET pin as does the 386 microprocessor, but rather the i486 microprocessor employs a simple 1.times. clock pin. This means that a 25 MHz i486 operates from a 25 MHz clock input. In further contrast to the 386 microprocessor, the i486 microprocessor uses an internal frequency doubling circuit to generate an internal 2.times. clock.
Due to this arrangement, the i486 microprocessor assumes that the proper CLK phasing is implicit in the one-times (1.times.) CLK pin input to the i486. Thus, the i486 microprocessor does not sample its RESET input to achieve clock phase correction. This difference in RESET/CLK phasing between the 386 microprocessor and the i486 microprocessor causes 1.times. clock synchronization difficulties in an application where a processor upgrade from a 386 microprocessor to an i486 microprocessor is attempted, when minimal change to the remaining circuitry of computer 10 or other computer is desired.